1. Field of the Invention
The present invention relates to a semiconductor integration circuit with restrained h.sub.FE dispersion.
2. Description of the Prior Art
Techniques have been proposed for obtaining a very fine base-emitter junction. For example, such a technique is disclosed in Japanese Patent Laid-Open Publication No. Hei 7-235547. The following describe the technique by reference to the accompanying drawings, FIGS. 1A through 1G.
First, as shown in FIG. 1A, an n-type semiconductor layer 11 to become a collector is formed on a p-type semiconductor substrate using an epitaxial growth method. A surface of the semiconductor layer 11 is selectively oxidized to form a LOCOS oxidized film 12 for separating elements. There is an n+-type buried layer 13. At a bottom of the LOCOS layer 12 is formed a p+-type separating region for making pn junction and separation of the n-type epitaxial layer.
A CVD oxidized film is deposited on the entire surface. Photo-etching is done to leave an insulation film 15 on the semiconductor layer to be emitter-diffused.
In turn, as shown in FIG. 1B, a surface of the semiconductor layer 11 not covered by the insulation film 15 has a polysilicon layer by the selective epitaxial growth method formed thereon to form a first silicon layer 16. After that, boron is ion-doped to an impurity for external base diffusion into the first silicon layer 16. Further, a silicon layer is deposited on the whole surface by the LPCVD method to form a second silicon layer 17.
Boron is then ion-injected to make the second silicon layer 17 conductive. The second silicon layer 17 is photo-etched to make the first and second silicon layers 16 and 17 form a base lead electrode 18. At the same time, the insulation film 15 is made open thereon to expose a top of the insulation film 15 (see FIG. 1C).
Next, as shown in FIG. 1D, the insulation film 15 is removed to form an opening 19 to expose the surface of the semiconductor layer 11. After that, as shown in FIG. 1E, the entire part is heat-oxidized to form a heat oxidized film 20 on the surface of the semiconductor layer 11 and surfaces of the first and second silicon layers 16 and 17. At the same time, the impurity doped from the first silicon layer 16 is diffused to form an external base region 21. Further, boron for forming an active base region is ion-injected without mask.
Next, as shown in FIG. 1F, a polysilicon layer is deposited on the entire surface. The layer is anisotropically dry-etched to form a side wall 22 on a side wall of an opening 19. After that, an HTO (high temperature oxide) 23 is formed on the entire surface. Further, the HTO is etch-backed to again expose the surface of the semiconductor layer 11 at the opening 19 again.
Finally, as shown in FIG. 1G, a polysilicon layer is deposited by the CVD method. The impurity for emitter diffusion is doped. After that the polysilicon layer is photo-etched to form an emitter lead electrode 24 at the opening 19. The entire substrate is heat-treated to diffuse the previously doped ion to form an active base region 25. At the same time, an emitter region 26 is formed by way of solid-phase diffusion from the emitter lead electrode 24.
An insulation layer is further adhered to the entire surface to form an emitter contact and base contact and form an emitter electrode and base electrode through a contact hole.
Using the method described above, a very small high-frequency transistor can be fabricated.
FIG. 2 shows structures of the first silicon layer 16 and base lead electrode 18 of FIGS. 1B to 1D integrated of polysilicon. Additionally a semiconductor integrated circuit device shown in FIG. 2 is formed in the process described above.
In the semiconductor integrated circuit device, after the step of forming the emitter lead electrode 24 (FIG. 1G), insulation film 27 is adhered to the whole surface as in the prior art described above to form an emitter contact 28, a base contact 29, and a collector contact 32 and form an emitter electrode 30, a base electrode 31, and a collector electrode 33.
As shown in FIG. 3, the lead electrode 24 on the emitter region 26 is etched, and then a recess 34 is formed on the lead electrode 24. As the diffusion source is removed, it becomes difficult to be uniform diffusion of the impurity. This causes a problem of differing depths of the emitter region 26.
The problem is present in the art described by reference to FIGS. 1A to 1G and the art in FIG. 2, and is described below by reference to FIG. 2.
As shown in FIG. 2, the insulation film 27 spread in the region in which the emitter contact 28, the base contact 29, and the collector contact 32 are formed, differs in the film thickness depending on position.
That is, area of the emitter contact 28 is covered with the insulation film 27, area of the base contact 29 has covered with the HTO film along with the insulation film 27, and area of the collector contact 32 is covered with the heat oxidized film 20 along with the insulation film 27. When the collector contact 32 and the base contact 29 are fully opened, the emitter lead electrode 24 is etched, forming a recess 34 on the electrode 24 because the film thickness of the area of emitter contact 28 is thinner than that of areas of the base and collector contact 29 and 32.
When a recess 34 is formed on a top of the emitter region 26, impurities to be doped to emitter are removed by the etching and the diffusion depth of the emitter diffusion region 26 becomes different. This makes it impossible to obtain a desired h.sub.FE and causes dispersion.